| category | description |
| Viewing rules | The schematic needs to be reviewed. Submitting a collective review requires a self-test to be completed to ensure that there are no low-level issues. |
| Viewing rules | The schematic should be reviewed with the company team and the experts that can be invited. |
| Viewing rules | All modification points need to be recorded after the first schematic is issued for collective review. |
| Viewing rules | The schematic of the official version needs to be tried by the manager before the investment. |
| Differential network | In the network of differential lines in the schematic diagram, P and N at the chip pins should correspond to P and N of the network commands. |
| Single network | All single networks in the schematic need to be confirmed one by one. |
| Empty network | All empty networks in the schematic need to be confirmed one by one. |
| grid | 1. In the schematic drawing, make sure that the grid settings are consistent. 2. There is no inconsistency in the grid minimum setting in the schematic diagram, causing the network to be disconnected. |
| Network attribute | Confirm whether the network is a global attribute or a local attribute |
| Package library | 1. The package of the device in the schematic diagram is consistent with the manual. 2. Whether the schematic device is a symbol of the standard library. |
| Drawing requirements | The package of the device in the schematic is identical to the manual. |
| Indicator light | Designed by default, the indicator light is lit by the power supply and the indicator light is turned off by the MCU. It is easy to visually judge the power supply problem or the MCU problem when the fault occurs. |
| Network port connector | Check the opening direction of the network port connector, whether it has an indicator light, and whether it has PoE |
| Network port transformer | Confirm that the transformer selection meets the requirements, such as with PoE |
| button | Confirm whether the button type is a straight button or a side button |
| Pull up | Avoid repeated pull-ups or pull-downs on the same network |
| OD door | The output pin of the OD gate or OC gate of the chip needs to be pulled up. |
| match | Requires series resistance at the beginning and end of high speed signals |
| Transistor | Transistor circuit needs to consider the flow capacity |
| Testability | Add holes to the critical circuit and chip near the board for testing |
| Connector foolproof | When selecting a connector, you need to select a model with a foolproof design. |
| simulation | Low-speed clock signal, the drive capability, matching mode, and interface timing of a device connected to the bus interface must be verified by simulation, such as MDC/MDIO, IIC, PCI, Local bus |
| simulation | Inductors and capacitors in the circuit use the appropriate Q value and can be simulated. |
| Timing | Verify that the power-up sequence meets the chip manual and recommended circuit requirements. |
| Timing | Verify that the power-down sequence meets the chip manual and recommended circuit requirements. |
| Timing | Verify that the reset timing meets the chip manual and recommended circuit requirements. |
| Reset switch | The design of the single-board button switch is to prevent the long-pressing button and the board from hanging. It is recommended that the button switch design only generate a short pulse width and low level. |
| Reset design | Reset signal design (1) Up and down according to chip requirements (2) Confirm the default state of chip reset (3) Peset signal parallel tens of PF capacitance filtering to optimize signal quality. (4) Reset signal to ensure model integrity. |
| Reset | All interfaces and optical modules are in reset by default. |
| Level matching | Different level standard interconnections, focusing on voltage, input and output thresholds, and matching methods. |
| Power consumption | Review the power consumption design of each chip in detail, calculate the maximum power consumption of each voltage of the board, and select a power supply with a certain margin. |
| Slow start | Hot-swap circuit requires slow start design |
| Magnetic beads | Small voltage and high current (amperes) value of the power output port of the magnetic beads, need to consider the magnetic bead pressure drop |
| Connector | Inter-board power connector flow capacity and pressure drop leave a pre-measure |
| Identification | Whether the stencil board and the motherboard socket network identifier are consistent, and the front and rear card cards have a one-to-one correspondence with the machine pin signals. |
| Level matching | One drive multiple signals should be impedance matched according to the simulation results to determine whether to add the start or end matching resistor |
| Matching level | The schematic design should pay attention to the description of the manufacturer's device data, and the input and output will have clear matching requirements. |
| Secondary tube | For diodes used in circuits such as control, detection, and power supply integration, it must be considered whether the diode reverse leakage current meets the design requirements. |
| MOS | Input/output pins that are not used in CMOS devices must be handled in accordance with the device manual. If not required by the manual, the manufacturer must confirm the processing method. |
| Warm feeling | Key components, especially temperatures, are monitored |
| 244/245 | The signals required for the up and down pulls need to be pulled down on the input and output of the bus driver after passing through the bus driver without the output hold function. |
| 244/245 | 244/245 If you do not have a hold function, you must pull down the unused input pins. |
| clock | The signal directly output from the crystal pin is forbidden to be directly driven by one drive. Multiple loads will affect the signal quality. It is recommended to use the one-to-one mode. |
| clock | The xt-out of the crystal is connected to the clock driver and requires 0402 series resistance. The resistance selection cannot affect the board vibration. |
| clock | The phase-locked loop circuit and the selection of parameters must be specially calculated. |
| clock | The clock loop filter ceramic capacitor is preferably an NPO dielectric capacitor. |
| clock | Confirm signal swing, jitter, etc. beyond the device requirements. |
| clock | Confirm that the clock device can fully meet the requirements in terms of center frequency, operating voltage, output level, duty cycle, phase and other indicators. |
| DDR | Memory interfaces such as DDR must have a clock frequency derating design. |
| DDR | For boards with higher reliability requirements, it is recommended to meet the ECC design rules in RAM development. |
| DDR | The DDR VTT power supply filter needs to match the Vtt resistor and the Lvbao capacitor. |
| PHY | MDC/MDIO adopts a one-drive multi-matching method. The main device is subjected to series resistance-"pull-up resistor-" string resistance to the slave device, and the series resistance is placed at both ends. |
| PHY | For 1-to-many control, the PHY needs to reserve address signals for control. |
| PHY | The power consumption of CAM and other chips varies greatly according to the access conditions and temperature. The design of the device manual should be carefully inspected to clarify the relationship between power consumption and the manufacturer's chip. |
| PHY | The optical module interface of the device is a 10nf capacitor connected in series with the optical module. The link does not need to be redesigned. |
| heat sink | When choosing a heat sink, consider the weight of the heat sink and how it is combined with the device. |
| I2C | When the device is interconnected through I2C, you can use the on-chip I2C module or the I2C module. |
| capacitance | When designing the RF-related part of the board, bypass and filter capacitors are required. Filter capacitors with different capacitance values ​​should be selected for different interference frequencies. |
| capacitance | When the capacitors are connected in parallel, the resonance point should be calculated or analyzed by simulation to avoid possible resonance problems. |
| capacitance | Filter capacitors are designed to focus on the effects of the control pins. |
| capacitance | How to use the unused pins requires reference to the design of the chip manual and the demo board to pay attention to whether the design of these pins is reasonable. |
| Characteristic impedance | Special requirements for the characteristic impedance of the PCB layout are required in the schematic or in the requirements document for the interconnection engineer. |
| Reset design | Key function devices should be reserved with a separate reset design. |
| Reset design | Many Flash have rst pins, in order to meet the requirements of the software function in the startup phase, |
| RF filtering | The power supply of the video amplifier should be designed with appropriate filter capacitors to prevent the power supply noise from affecting the quality of the RF signal. |
| RF filtering | Power supply and power circuit design is the choice of application power to consider the power characteristics of the resistor. |
| Testability | Some functional modules need to be kept in a long-term state, which is good for hardware testing. |
| Radio frequency circuit | Whether the DC bias circuit needs to be enabled to control whether the voltage accuracy meets the requirements of the amplifier. |
| Radio frequency circuit | It is guaranteed that the maximum RF peak power that the front stage may output is less than about 3 dB of the maximum limit input power of the downstream cascading device, and attention should be paid to the influence of signal peak and overshoot on the device over power. |
| Radio frequency circuit | The central thermal pad of the RF device power amplifier must be grounded on the schematic. |
| Radio frequency circuit | With on/off RF device function, the isolation has problems in the off state, the isolation affects the interference of the transceiver, and the interference signal needs to be kept within a reasonable level, otherwise the chip will work normally. |
| Radio frequency circuit | PA's RF transmitter link PA peripheral circuit positive price negative feedback design prevents burning PA. |
| Radio frequency circuit | The RF receiving circuit needs to reserve a PI type position between the receiver and the chip to debug the receiving sensitivity. |
| power supply | Ensure that all power conversion modules OCP/OVP points (overcurrent protection points and overvoltage protection points) are set correctly |
| power supply | Whether the load capacity of the power supply is sufficient, whether the number of phases is sufficient, can provide enough current and power to the CPU, Chipset, etc. (1 phase is calculated according to the maximum 20A, conservative 15A) |
| power supply | PWM single-phase frequency range is 200K-600K; integrated MOS can reach 1MHz |
| power supply | Ripple current of the input capacitor (refer to 2700mA); small capacitance Ripple Current will cause the capacitor to heat up, affecting the life |
| power supply | Is the ESR of the output capacitor small enough? |
| power supply | Whether the withstand voltage of the capacitor is satisfied, while satisfying the derating |
| power supply | H-MOS on-time is short; L-MOS on-time is long |
| power supply | H-Side MOSFET should choose fast conduction speed |
| power supply | L-Side MOSFET should choose Rds(on) low |
| power supply | The loss of the linear power supply P = Δv * i, generally, the power loss of a LDO can withstand Pmax * Junction = device Temp, to ensure that the sum of the device temp and the environment Temp is less than 80% of the maximum operating temperature of the MOS. |
| power supply | Uniform power and land names on the board should be unified |
| power supply | The single-phase PWM driver's BOOT pin and phase are terminated with a 0.1uF capacitor. Check the BOOT capacitor for a withstand voltage of 50V. After the H-MOS is turned on, the BOOT Pin voltage is 24V and the Phase 12V. |
| power supply | A 0 ohm resistor is reserved on the H-side Gate to prevent the High side MOS from being broken down due to excessive Vgs |
| power supply | The feedback circuit setting is accurate; the feedback voltage calculation formula is annotated on the circuit. |
| power supply | The GND and AGND circuits should be separated, but the last connection is made through one point. If the chipset's AGND current is very large, it can be directly connected to GND. It is not necessary to connect 0OHM, otherwise the current will not be enough. |
| power supply | PWROK pull-up should be pulled up with the corresponding power supply. |
| power supply | After some module lines are copied over, you need to pay attention to the AGND attribute to be changed. It is best to give the net name. For example, you will often encounter the same name as the two A1 of P1V1. |
| power supply | Confirm the inductor package and check if the saturation current meets the circuit requirements. The larger the inductor package, the stronger the overcurrent capability, and the saturation current of the inductor should be greater than the OCP current of the circuit. |
| power supply | Confirm the compensation line to ensure sufficient crossover frequency and phase margin. |
| power supply | Check if the maximum differential voltage of the LDO meets the requirements of the device (input voltage range and output voltage range) |
| FPGA | Confirm that the logic level of the input and output is correct; level type: GTL, OD, LVCMOS33, LVCOM25, LVDS, etc. Verify that the logic levels between the chip and the CPLD/FPGA match to avoid inconsistencies between the two sides. |
| FPGA | When the GPIO signal of the CPLD is used as the output pin to control the timing, the pin needs to be pulled down through the 4.7K to 10K resistor. |
| FPGA | The JTAG interface of the CPLD needs to be connected to the Header. Note that the Piner definition of the Header complies with the requirements of the programmer, and the JTAG signal reserves the ESD protection circuit. |
| FPGA | The unused GPIO pins are connected to the LEDs, usually 3-4 LEDs. |
| FPGA | For the same function, the GPIO should only use the same Pin (except the Reset signal). |
| FPGA | The level of different banks is related to the VCCIO level of this bank. |
| FPGA | When the FPGA is connected to the ROM, you need to mark the sequence of 1, 2, and 3 in the schematic diagram (there may be problems in the sequence that cannot be programmed). Ensure that the interface level between the signal connections is correct, whether a levelshift design is required |
| FPGA | CPLD core and IO power timing, generally require core power to be earlier than IO power, otherwise, the output signal needs to add a pull-down resistor. (In general, the core power is earlier than the IO voltage. After the Core is up, the IO state can be fixed. For specific requirements, refer to the manufacturer's device data.) |
| FPGA | If the MGT Bank of the FPGA is not in use, the RX signal needs to be grounded. |
| FPGA | MGT Bank refers to a bank that can be configured as a high-speed interface, such as GTL of xilinx, GTX interface bank, and RX signal processing when not in use. |
| FPGA | The CPLD requirements file must be provided to the CPLD programmer during the principle design. |
| FPGA | The input and output states of each pin must be specified in the CPLD requirements file. |
| FPGA | For CPLD, use as little as possible of sequential logic, use combinational logic, and replace complex logic with simple logic as much as possible. |
| FPGA | The logic requirements provided by the designer should avoid competition and risk, that is, use the signal output by the CPLD to make other logic input decisions. |
| FPGA | There are design requirements to support I2C. It is necessary to plan the system I2C topology in advance, and consider the reserved logic space when selecting the chip. (BMC if the I2C resources are sufficient, the CPLD occupies a separate set of I2C buses) |
| Connector | The bandwidth of the high-speed connector should be 1.5-2 times |
| Connector | Confirm the way the connector is defined on the PCB |
| Connector | Whether the definition of the corresponding pin signal of the two connector boards is the same. For multiple board interconnections, it is necessary to confirm whether the physical position of the corresponding connector is correct. |
| Connector | According to the thickness of the plate to determine whether the welding piece and crimping device can be selected |
| Connector | Generally, the connector should be careful that the female end has long and short pins, so the female terminal needs to define the power supply and GND. |
| Connector | High-speed signal connector, the GND pin around the high-speed signal must be grounded |
| Connector | High-speed signal connector, when defining the signal, pay attention to the distribution of TX and RX on the connector, avoiding TX/RX mixing (avoiding cross talk) |
| Connector | As an interface composed of two connectors, you need to select the same manufacturer, the same type of connector |
| Connector | When the SMD connector is selected, it has a flat surface on it, which is convenient for the high-speed machine nozzle of the project to be sucked off. Packing prefers trays, not tubular. |
| Connector | Try to be unified as a soldering device or a crimping device |
| Connector | Pay attention to the choice of pin length |
| Connector | Be sure to provide a sequence of connector positions before entering the layout layout. |
| Connector | When selecting the connector, choose the common material (more than two Sources) to ensure a certain substitutability. |
| Connector | The thickness-to-diameter ratio of the PCB needs to be considered when selecting the connector (cannot exceed 10:1) |
| Connector | Pay attention to the connector color when selecting the network port connector. The color difference will affect the appearance perception of the product. |
| Connector | For different speeds and types of interfaces, such as 10GE, GE port, FE port, control port, and debug port, you can distinguish between different colors of the mask. |
| Connector | When selecting the connector, you need to pay attention to whether there is a positioning pin. When there is no positioning pin, the positioning may occur. |
| Connector | When selecting the connector, you need to pay attention to the relationship between the length of the pin and the thickness of the PCB. If the pin is too long, the pin needs to be processed when the board is finished. The pin is too short (such as the positioning pin). Awkward and other phenomena. |
| clock | Clock signal (except for the Differential Signal), reserve the position of the capacitor that can adjust the EMI, usually 10pF. |
| clock | The clock signal of the PCI-E2.0 slot is recommended to be the same as the control chip. |
| clock | When Clockgen or Clock Buffer is powered by SYS, you should pay attention to whether the clock signal of the chip such as network card or CPLD needs a separate clock source. |
| clock | The voltage on the SMbus interface of all Clockgen and Clock Buffer should be the same as the power supply of the IC. |
| clock | When the level of the crystal oscillator or clock buffer output does not match the level required by the IC, AC coupling and impedance matching circuits need to be added, and attention should be paid to whether the SWING and CROSSPOINT settings are correct. |
| clock | Note the clock signal output level of Ossilater. If it is LVPECL, externally need to add 150ohm resistor to ground. For transmit stage coupled logic, a ground return path is required at the periphery. |
| clock | The crystal oscillator of the CPU should be arranged as close as possible to the crystal input pin. The passive crystal oscillator should add tens of picofarads of capacitance; the active crystal oscillator can directly direct the signal to the crystal input pin of the CPU. |
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