All beginners know that the interrupt mode of the processor is edge trigger and level trigger.
Edge triggering is rarely used, and falling edge triggering is the main method. When the device completes a data, it will output a falling edge to trigger the processor. The level trigger is to output a level, and will maintain this level, until the system processes or clears the interrupt before outputting another level.
In FPGA, AXI bus or AVALON bus is often encountered, and the bus interface is often level triggered. If the fpga end is the master end. Need to design interrupt trigger state machine and clear interrupt operation.
always@(clk)
begin
if (rst)
...
else if(irq)
state <= irq_state;
else case (state)
....
end
There is no problem with the above code visually, but the problem is that irq is level triggered, the code will always be in if (irq) and will not enter the case statement, this will cause irq to be unable to clear all the time, and the code will always die in if (irq) in.
To solve the above methods, one is to get the irq edge trigger, if the high level is valid, it is the rising edge. If it is low, it is a falling edge.
So the code is
if (rst)
else if (irq_rising)
...
else case(state)
This state can also cause a problem, that is, if you enter the normal state and transition to this state, it will cause all the data to be messed up. Of course, it is better to use polling status opportunities. That is to say, use polling irq in the state machine to see if it is high.
case(state)
idle:
normal_irq_sw:
begin
if (normal_req)
. . .
else if (irq)
state ＜=irq——state
end
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