1 Introduction
With the growth of market demand, the level of integration and technology of VLSI circuits has continued to increase, and it has become possible to complete system-level design on a single chip. FPGA's inherent parallel computing processing capabilities, making it able to provide a variety of digital computing requires a large number of complex operations, suitable for the design of some of the processing speed and real-time requirements of a higher intelligent controller. In recent years, FPGA-based controller design studies have been active based on VHDL descriptions. For example, Toralba et al. completed FPGA implementation of a fuzzy logic controller with 4 inputs, 12 memberships, and 64 rules [1], Cirstea et al. A fuzzy controller based on FPGA was successfully used for transmission control [2]. In addition, due to the flexibility and versatility of FPGA design, FPGA-based controllers have high development efficiency, low cost, and short time-to-market.
Due to the extensive use of FPGAs in intelligent controllers, post-design testing has become a major consideration for designers in the development process. At the same time, a good test method can not only find problems in the design as early as possible, but also Improve design reliability. Currently, intelligent controller testing based on VHDL description generally verifies the correctness of its logic design through open-loop timing simulation. However, for some intelligent controllers with input excitation signals that are not fixed or many, open-loop timing simulation is not accurate. Analog controller excitation input signal. Therefore, this paper presents a closed loop timing simulation test method based on Quartus II, DSP Builder, and Modelsim on the basis of open loop timing simulation. The closed loop test method is further studied with the help of a specific intelligent controller design. the study.
2 FPGA Design and Test Platform
Quartus II4.0, DSP Builder3.0, and Modelsim SE6.0 were used as FPGA design and test platforms.
QuartusII4.0 is Altera's fourth-generation programmable logic device integrated development environment, providing input from the design, design compilation,
Functional simulation, design processing, timing simulation, and device programming. At the same time, it can generate and identify EDIF netlist files, VHDL netlist files, and Verilog HDL netlist files, and provides a convenient interface for other EDA tools. Other EDA tools can be automatically run on top, including Synplicity's Synplify/Synplify Pro, LeonardoSpectrum from Exemplar Logic, a subsidiary of Mentor Graphics, and FPGA Compiler II from Synopsys. These synthesis software can translate VHDL/Verilog design software into standard netlist files for selected devices with high efficiency. In addition, QuartusII 4.0 also integrates a SOPC Builder development tool to support SOPC development [3].
DSP Builder appears in the form of Blockset of Matlab/Simulink, and can be graphically designed and simulated in Simulink. At the same time, Matlab/Simulink design files (.mdl) can be converted to corresponding VHDL files (.vhd) through the Signal Compiler, and Used to control synthesis and compilation of TCL scripts [4].
Mentor Graphics' Modelsim is a better simulation tool in the industry. It has powerful simulation capabilities, supports analog waveform display, and has a friendly graphical interface, with structures, signals, waveforms, processes, and data flow.
Through the comprehensive use of the above three platforms, the design process can be well planned, the advantages of each tool can be fully utilized, the development efficiency can be improved, and the obtained test results can be more reliable.
3 VHDL design and test features of intelligent controller
Take fuzzy self-tuning PID controller as an example, the positional control algorithm is:
Ui = Kp ei+Ki T∑ei+Kd/T(ei-ei-1)+u0 3.1
Where: Kp = kp + tp & TImes; â–³ Kp, Ki = ki + TI & TImes; â–³ Ki, Kd = kd + td & TImes; â–³ Kd is the real-time parameters of the PID controller; â–³ Kp, â–³ Ki, â–³ Kd is the correction value obtained by fuzzy inference. The fuzzy reasoning process adopts Mamdani's direct reasoning method and adopts the centroid method to obtain the corresponding final exact value.
Based on VHDL description of fuzzy self-tuning PID controller design using top-down design method, in the RTL level of each unit module design description, with the structure of VHDL units through the unit mapping (PORT MAP) linked together to form the entire controller chip. The core of the controller chip is the control and operation unit, which involves basic data processing, storage, and I/O control. Its top-level module circuit schematic shown in Figure 1.
Figure 1 Controller top-level module circuit schematic
Among them: control: the control module, generates the read-write address of the memory data; ram: the storage module, stores the data collected from the outside; accum: accumulates the module, accumulates 10 times, reads the data into the memory; max_min: asks the Max/Min module Calculate the maximum and minimum value of the collected data; sub: subtract module, remove Max/Min, average_8: filtering module, perform 8 average filtering on the eliminated data; compare: compare module, compare with given value, Deviation e;delay: delay module, the rate of change of the deviation generated ec; fpid: fuzzy self-tuning PID controller module, generating the controller output signal.
In this system, A/D adopts AD574A, its maximum conversion speed is 35μs, and the conversion accuracy is less than or equal to 0.05%. When designing an A/D I/O module using VHDL, a state machine description is used. The state machine is divided into five states: STATE0: A/D 574 is initialized; STATE1: A chip select signal is generated and the conversion is started; STATE2: STATUS is monitored and the state is switched; STATE3: The 8-bit output data is valid; STATE4: is the Lock signal. Latch data.
The intelligent controller test feature based on VHDL language description is: The controller module can be used as an independent module to test the correctness of its logic function through the open-loop timing test reference. However, for the control system, we are more concerned with the time response process of the system output under the action of a typical input signal, including dynamic processes and steady-state processes. Therefore, it is particularly necessary to use closed-loop timing testing.
4 FPGA-based intelligent controller open-loop timing test
The open loop timing test mechanism of the intelligent controller based on FPGA is: through connecting the incentive entity and the measuring module, the output response value of the measured module is compared with the expected value to verify whether the controller design meets the design requirements. The designer can use the Quartus II software. The waveform editor generates a vector waveform file (.vwf) that acts as an emulator stimulus. It is also possible to use a text-based vector file (.vec) as the stimulus for the simulator. Among them VWF uses the graphical waveform form to describe the input vector of the emulator and the output of the simulation, and VEC uses a special format file to add excitation to the input signal and vector in the module [5]. This is the current design. The most commonly used test method. Fuzzy open-loop timing simulation test of self-tuning PID controller is shown in Figure 2.
Figure 2 controller open-loop timing simulation
Figure 2 shows the closed-loop output timing simulation results of a fuzzy auto-tuning PID controller based on Altera's FPGA device EP20K200EQC240-1.
Where: clk: system clock; clkc: controller sampling clock; reset: system reset signal; e: deviation; ec: rate of change of deviation; u: controller output.
Timing simulation result parameters: Total logic elements: 1092 / 8,320 (25 %); Total memory bits: 4096 / 106,496 (3%); Clk setup: 38.86 MHz; Clkc setup: 221.39 MHz; Tsu: 8.864 ns; Tco: 7.809 ns .
In Figure 2, the controller's excitation signal deviation e and deviation rate of change ec are manually edited by the waveform editor. The input is cumbersome. Their values ​​are obtained by means of the MATLAB simulation curve, and therefore cannot completely simulate the real-time performance of the intelligent controller. Incentive signal. In order to better simulate the input behavior of the controller and make the test result more reliable, based on the above test, this paper presents a new closed-loop timing test method based on the FPGA design tools Quartus II, DSP Builder and Modelsim.
5 FPGA-based intelligent controller closed-loop timing test
In the design of automatic control system, the design and test of the controller usually adopt a closed-loop control system. The output of the observation object is used to judge whether the controller performance meets the design requirements. DSP Builder, a digital signal processing tool introduced by Altera Corporation, in conjunction with the MathWorks Matlab and Simulink, provides a new test method for designing in Quartus II. The test process used in this study is as follows: First, use DSP Builder to build the test module in Simulink of Matlab. After the operation is correct, use the Signal Compiler to convert the (.mdl) file into the TCL script file and VHDL file that Modelsim can identify. , Set the generated VHDL file and TCL script. Finally, run the test file in Modelsim to see the test results. The module diagram of fuzzy auto-tuning PID controller under DSP Builder is shown in Figure 3. In the figure, the fpid module is a user-defined module, which is imported through the DSP Builder's SubSystemBuilder module. Using this module, the input and output pin signals of the VHDL design file in the Quartus II software can be easily introduced into the Simulink system.
Fig. 3 Module test diagram of fuzzy self-tuning PID controller under DSP Builder
Run the Signal Compiler to generate the TCL script file used in Modelsim, because the user-defined modules added in Simulink appear in the form of black boxes. Therefore, in this test environment, the individual of the fuzzy auto-tuning PID controller should be The module file is added to the TCL script file. For example, to add the submodule file pid.vhd to the TCL script file, use vcom -93 -explicit -work work "$workdir/pid.vhd".
There are two things to note when using DSP Builder:
(1) If you do not use the phase-locked loop PLL from the Rate Change library, the DSP Builder will use synchronous design rules in the process of converting the Simulink design into a hardware system, ie all DSP Builder timing modules in the design system (eg, The Delay1 module in Figure 3) operates synchronously with the rising edge of a single clock, which is the sampling frequency of the entire system. For these modules, their clock pins are not directly displayed on the Simulink design diagram. However, when using the Signal Compiler to convert the design into a VHDL file, the system will automatically connect the clock pins of the timing module together. The system's single clock connection.
(2) When a custom VHDL design entity is added to the DSP Builder design system, synchronous reset and clock input signals must be defined in the entity even if the synchronous reset and clock signals have been used in the original design. Also, these two input signals must be connected to the global clock pin and global synchronization clear pin of the target device. If the entity does not require a clock or Global Synchro Clear, these input signals should also be defined, but do not connect.
Taking the controlled object G(s)=4.71×e-0.15s/(0.4s+1)(1.2s+1) as an example, taking into account the influence of A/D and D/A, a zero-order keeper is added (1 -e-TS)/S, the output curve of the closed-loop control system in Modelsim is shown in Fig. 4. The set value of the system is 127 (relative gain is 0.992), and the output value rises from 0 to peak value 148 (relative gain is 1.156). After quickly falling back, and finally stable at 127, the test results and MATLAB simulation results are basically the same.
Figure 4 System closed-loop output curve
6 Conclusion
(1) The intelligent controller based on FPGA has the advantages of flexible design, online adjustment, high reliability and short development cycle. Particularly suitable for small and medium-sized systems.
(2) VHDL design of intelligent controller using Quartus II, closed-loop testing of designs in Quartus II by DSP Builder and Modelsim, solves the input source of the test sample and the input sample extraction problem of the controller, and can effectively simulate and control The input behavior of the instrument improves the design and test flexibility. At the same time, the test results are reliable and convincing.
(3) Using DSP Builder and Modelsim to get rid of the previous test habits, the controller's excitation input signal can easily call the Simulink module, the object can also be flexibly changed according to needs, do not need to use VHDL language, and Modelsim support The analog waveform display of the signal allows us to see the most intuitive graphics.
(4) Test plays an important role in system design. It runs through the entire design, using closed-loop timing testing method, and combining DSP Builder and Modelsim to complete testing of various stages of the intelligent controller. Experimental verification is a better test method. Suitable for designs such as controllers that require closed-loop inspection of their control quality.
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