Abstract: In the precision measurement of astronomical optics, nano-precision piezoelectric ceramic sensors are often used as micro-displacement actuators to drive various precision displacements. In order to further improve its acquisition accuracy and real-time performance, an acquisition system based on Zynq7000 dual-core ARM processor was designed. In the PL part of Zynq, data acquisition and OLED display IP core are realized. CPU0 is used as the main processor to realize system control and piezoelectric ceramic voltage collection. The acquisition frequency reaches 30 kHz and the data resolution is one in ten million. Absolute accuracy reaches 10 μV; CPU1 acts as a slave processor and displays information on the OLED in real time.
Introduction Piezoelectric (PZT) has become one of the most widely used materials for astronomical optical precision measurement in recent years due to its unique small size, fast response, high precision and micro-motion function. Therefore, its acquisition accuracy and real-time performance is one of its key technologies. This design uses Xilinx's Zynq7000 dual-core ARM processor as the design platform to achieve high-speed and high-accuracy acquisition of PZT. Zynq is a new architecture processor with ARM as the core and FPGA as the programmable peripheral. Its ARM core is an AMP system composed of two CortexA9 CPUs.
At present, most of the PZT acquisition systems use the acquisition card under the PC or the system design similar to the single-chip microcomputer. Due to the poor real-time performance of the PC system, the data processing capability of the single-chip microcomputer is relatively weak, and it is difficult to meet the similarity of the astronomical optical measurement system. Real-time requirements, using the PL part of Zynq for data acquisition, can reach the order of μs. Using the PS part of Zynq for data storage, data processing and communication, real-time performance can also be on the order of μs.
1 data acquisition and OLED display IP core design 1.1 OLED display IP core design
The ZedBoard development board uses Inteltronic /Wisechip's OLED display module UG2832HSWEG04, and the drive circuit uses Solomon's SSD1306 chip. The OLED is controlled by SPI mode. The signal lines and power lines used in the SPI mode are as follows:
1 RST (RES): Hard reset OLED.
2 DC: Command/data flag.
3 SCLK: Serial clock line.
4 SDIN: Serial data line.
5 VDD: Logic circuit power supply.
6 VBAT: DC/DC converter circuit power supply.
7 OLED display IP core refers to the configuration of related peripherals in the PL, hooked into the PS, used as a peripheral part of the PS part.
You only need to use Xilinx's embedded tool XPS to generate hardware systems. The main process is as follows:
1 Generate the smallest hardware system of Zynq according to the XPS tool design flow.
2 In the smallest hardware system, add the peripheral IP my_oled, add a 6-bit register, and each bit corresponds to the SPI pin.
3 Set the relevant pin and direction information in the MPD file generated by the system.
4 In the my_oled.vhd file generated by the system, the port design is done in VHDL language.
5 In the user_logic.v file generated by the system, the Verilog language is used for logic design, and the register and SPI corresponding port are connected and read in real time.
1.2 Data Acquisition IP Core Design Because piezoelectric ceramics have very high precision, the ADS1256 is a multiplexed 24-bit very low noise ΔΣ ADC with a high precision ADS1256 conversion chip. Its theoretical sampling accuracy is one of 16 777 216, and the measurement voltage range is -5 to +5 V. Therefore, its theoretical accuracy is 1.6 μV, and the actual test reaches the order of 10 μV.
ADS1256 and Zynq are SPI serial interfaces composed of SCLK, DIN, DOUT, DRDY, CS and RST. Since they are not on the ZedBoard development board, the above 6 pins need to be connected through the JA and JB interfaces on the board.
The data acquisition IP core design is mainly to complete the 6-pin connection, as well as the command and data transmission and clock setting of the A/D conversion process. The design process is completely consistent with the OLED display IP core design process.
2 Zynq dual core operating principleZynq is a scalable processing platform, and its boot process is completely different from FPGA, and similar to traditional ARM processors.
After the system is powered on, the 0th stage startup code determines the startup mode, downloads the first stage startup code amp_fsbl.elf to the DDR, and starts execution. The FSBL configures the hardware bitstream file and loads the CPU0 executable file and the CPU1 executable file to the link address corresponding to the DDR. At this stage, all code is executed in CPU0, then the first executable file app_cpu0.elf is executed, the application execution address to be executed on CPU1 is written to the 0xFFFF FFF0 address of OCM, and then the SEV assembly instruction is executed to activate CPU1. . After CPU1 is activated, it will read its value from the 0xFFFF FFF0 address of OCM. The value is the address at which CPU1 executes the executable program, and the CPU1 application will execute from this address.
CPU0 and CPU1 communicate with each other through the OCM's 0xFFFF 0000 address as shared memory.
Zynq is an AMP architecture. CPU0 and CPU1 each occupy separate DDR space. The DDR address occupied by CPU0 is 0x0010 0000~0x001F FFFF, and the address space used by CPU1 is 0x0020 0000~0x002F FFFF. The dual core operating principle is shown in Figure 1.
Figure 1 Dual-core operating principle
3 software designThe software design mainly includes the CPU0 application and the CPU1 application. The CPU0 part mainly implements system initialization, starts the CPU 1, reads the A/D converted data, and performs preliminary processing on the data.
After loading the CPU0 application, the FSBL jumps to 0x0010 0000 to execute the CPU0 program. First, configure the MMU and close the Cache so that the OCM physical address is 0xFFFF 0000~0xFFFF FFFF and 0x0000 0000~0x0002 FFFF.
After the Cache is closed, CPU0 executes the SEV assembly instruction, activates CPU1, reads the CPU1 application address from the 0xFFFF FFF0 address of CPU1 to OCM, and starts executing the application of CPU1.
The ADS1256 converted data is read and compared with the ADS1256 converted values. If it is greater than 0xFF, the piezoelectric ceramic is considered to be abnormal. Set COM_VAL=1, and wait for CPU1 to display the abnormal information on the OLED. The flow chart is shown in Figure 2:
Figure 2 CPU0 program flow chart
After CPU1 is activated, it will execute the application from the 0x00200000 address of DDR. Since Zynq is an AMP architecture, each CPU uses resources independently. Therefore, in CPU1, you still need to set the MMU and turn off the Cache.
After the Cache is closed, CPU1 reads the shared memory COM_VAL variable. If its value is 0, it means that the piezoceramic works normally and displays the correct information on the OLED. If COM_VAL=1, it means that the piezoelectric ceramic works abnormally and will display abnormal information in the OLED. The flow chart is shown in Figure 3.
Figure 3 CPU1 program flow chart
4 Experimental resultsAfter the hardware and software design is completed, the hardware bit stream needs to be configured to the PL part of Zynq, and the software part is downloaded to the DDR for operation. Use Xilinx's BootGen tool to combine FSBL files, bit files, CPU0 files, and CPU1 files into related headers to generate a legal image BOOT.BIN file that can be recognized by Zynq. Copy BOOT.BIN to the SD card, set the ZedBoard to the SD card to start, insert the SD card into the SD card slot, and after power-on, you will see the OLED display piezoelectric ceramic working status information.
In the experiment, the piezoelectric ceramics randomly read the data collected by the partial A/D at a fixed position. As shown in Table 1, it can be seen that the acquisition accuracy is on the order of 10 μV.
Tested with a desktop multimeter at 2.5 V. The experimental results show that the A/D acquisition accuracy is up to 10 μV, which is consistent with the high-precision benchtop multimeter measurement, indicating that the acquisition results are correct.
Conclusion Using high-precision ADS1256 converter and Zynq high-speed processing platform, dual-core ARM parallel operation data acquisition and real-time display functions are realized. After 24 hours of uninterrupted testing, the system is stable and can meet the requirements of high-speed and high-precision piezoelectric ceramic sensor acquisition systems.
references
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