FPGA dilemma mixed system architecture to solve

In new semiconductor manufacturing processes, FPGAs are often one of the first devices to be adopted, validated, and optimized. Misha Burich, senior vice president and chief technology officer of Altera, believes that the industry is facing a dilemma of flexibility and efficiency. The "hybrid system architecture" with integrated microprocessor + DSP + dedicated IP + programmable architecture is expected to play a huge advantage. Take the Altera StraTIx V FPGA as an example, with a highly flexible 28Gbps transceiver, but in today's system-oriented environment, this is not enough. Because the serial link also requires a controller that is fast enough, the controller requires a high speed on-chip bus and cache. At the same time, all of these modules must also meet energy requirements.

High-speed serial links are not the only instance. Many of today's system designs include FPGAs and one or more 32-bit embedded processors. Is it to purchase the CPU as a dedicated standard product IC or advanced controller, or to implement the CPU in the FPGA using a soft core in a programmable architecture, or to select an FPGA supporting a hard ARM processor such as a SoC FPGA in a cache, a DRAM controller, and How can the accelerators be divided to achieve the most bandwidth-intensive data flow? These answers ultimately depend on the specific application. No matter how convenient it is for FPGA vendors, there is no single solution for all users.

In 2012, many very competitive system design teams will be highly specialized, requiring a full IP core, automated IP assembly tools and a complete reference design, requiring IC vendors to provide the required system platform. Altera can't just serve a user with a single chip and a single chip with different capacity/pinout outputs. To meet the needs of different applications, FPGA vendors must provide transceiver design choices, implement interface controllers, internal memory block capacity, speed and power, hardware architecture for internal bus architecture, and cover synthesis/emulation/timing analysis, system interconnection Development environment based on C language programming tools, DSP programming, embedded software tools.

Misha Burich said that Altera has noticed new application opportunities for some FPGA products, including hardware acceleration for servers, solid state drives, and SoC FPGAs for in-vehicle assisted driving. The 3D package and OpenCL will be key support technologies for silicon fusion. Recently, Altera announced the use of TSMC's CoWoS (Base Wafer Chip Production) technology to develop the world's first 3D IC test chip capable of integrating Heterogeneous technology. “It’s users and applications that are driving the integration of heterogeneous systems into a single package,” said Misha Burich. “This innovation combines a variety of different chip technologies, including analog, logic and memory, on a single chip. Improve system performance and significantly reduce system power and cost on a smaller package."

In programming FPGAs with OpenCL, Altera has reportedly developed a software tool in the prototype stage that can perform OpenCL code, compile, etc. on the FPGA, with sufficient performance to produce time-to-market and performance. With a positive impact, the software is currently being introduced and tested in a variety of companies in the vertical market, such as high performance computing, meteorological and financial modeling, radar and medical. According to Altera, the new software is still in the definition phase due to the diverse needs of the vertical market and the software is optimizing the code to improve functionality. "For the moment, we're just releasing a program, not a product, and hope that future versions of the OpenCL specification will add support for the stream memory interface used by FPGAs," said Misha Burich.

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