Q: With zero foundation, if I want to learn FPGA, where should I start? What tutorial should I watch? What learning and development boards should I use? What books are you reading?
If you want to do it quickly, then watch the video online, this is mainly for the application, and you can get your board running within an hour. In the early days, it is easy to get up and learn and use it. Even if there is no systematic theoretical support in the later stage, it will be a bit difficult, especially for large projects. It is a complete tragedy. It can be done in China, Zhou Ligong is one of them, and so can Amy Electronics. Both of them have learning boards, but the latter's tutorials are copied from the former's. The former has a solid foundation, and you can buy the former if your funds are not tight. If it is quick, the number of e-books must be a must, it is better to learn while reading, and the rest of the books can be bought in moderation.
In fact, as long as you are interested, learn slowly, and it is not difficult to get started, you can buy the board online. EDA365 is a very good purchasing platform.
High-energy early warning of knowledge points ahead
(A brief summary of a few points first:)
1. Look at the code and build a model
Only by establishing a logical model in one's mind and understanding the basis of the implementation of the internal logic structure of the FPGA can we understand why the overall ideas of writing Verilog and writing C are different, and we can understand the difference in the design methods of sequential execution languages ​​and parallel execution languages. . When you see a simple program, you should think of what kind of functional circuit.
2. Use mathematical thinking to simplify design logic
Learning FPGA is not only important for logical thinking, but good mathematical thinking can also simplify your design. Therefore, those children's shoes who have a headache when they see high numbers need to pay attention to this course. For a simple example, for example, there are two 32-bit data X[31:0] and Y[31:0] multiplied. Of course, both Altera and Xilinx have ready-made multiplier IP cores that can be called, which is also the easiest method, but two 32-bit multipliers will consume a lot of resources. So is there a way to save resources and be less complicated? We can modify it slightly:
Split X[31:0] into two parts X1[15:0] and X2[15:0], let X1[15:0]=X[31:16], X2[15:0]=X[15 :0], then X1 is shifted to the left by 16 bits and added to X2 to obtain X; Y[31:0] is also split into two parts, Y1[15:0] and Y2[15:0], so that Y1[15: 0]=Y[31:16], Y2[15:0]=Y[15:0], then Y1 is shifted left by 16 bits and added to Y2 to obtain Y; then the multiplication of X and Y can be converted into X1 and X2 are multiplied by Y1 and Y2 respectively, so that a 32bit*32bit multiplication operation is converted into four 16bit*16bit multiplication operations and three 32bit addition operations. After the conversion, the occupied resources will be reduced a lot. Interested children's shoes may wish to take a comprehensive look and see how much difference between the two.
3. The relationship between clock and flip-flop
The phrase "the clock is the controller of sequential circuits" is so classic that it can be said to be the holy grail of FPGA design. The design of FPGA is mainly based on sequential circuits, because no matter how complicated the combinational logic circuit is, it cannot change too many tricks, and it is not too difficult to understand. But the sequential circuit is different. All its actions are triggered by the rhythm of the clock. It can be said that the clock is the controller of the entire circuit. If the control is not good, the circuit function will be chaotic.
For example, the clock is equivalent to the heart of the human body. Every time it beats, it triggers a CLK, which supplies blood to various organs of the body and maintains the normal operation of the body. The normal operation of each organ system requires the composition of tissue cells, then triggering The organ can be compared to the basic unit of tissue cells. The clock of the sequential logic circuit is the "engine" that controls the state transition of the sequential logic circuit. Without it, the sequential logic circuit cannot work normally, because the sequential logic circuit mainly uses the flip-flop to store the state of the circuit, and the state transition of the flip-flop requires the rise of the clock. or falling edge! This shows the core role of the clock in sequential circuits!
Finally, let me briefly talk about my experience. It boils down to more practice, more thinking, and more questions. Practice brings true knowledge, and it is better to practice it yourself after reading other people's plans 100 times. The motivation for practice comes from interest on the one hand, and pressure on the other, and I personally think the latter is more important. It is easy to form pressure when there is a demand, which means that it is better to exercise in actual project development, rather than learning for the sake of learning. In the process of practice, you need to think more, think about the reasons for the problem, and ask a few more reasons after the problem is solved. This is also the process of accumulating experience. methods are written in. In the end, I have to ask more questions. After thinking about the problem, I have to ask if I can’t solve it. After all, the power of the individual is limited. You can ask your classmates, colleagues, search engines, or netizens. may help you solve the problem quickly.
Why do a large number of people find FPGA difficult to learn?
1. Not familiar with the internal structure of FPGA and basic principles of programmable logic devices
Why are FPGAs programmable? I'm afraid many rookies don't know, and they don't want to know. Because they felt it was irrelevant. They subconsciously think that programming is like writing software. The idea of ​​software programming is deeply ingrained, and seeing Verilog or VHDL is like seeing C language or other software programming languages. One by one read, one by one analysis. If these rookies always refuse to understand why FPGAs are programmable, and do not understand the internal structure of FPGAs, it may be impossible to learn FPGAs. Although the EDA software is very advanced now, it is possible to synthesize something just like writing software, but maybe only God knows what the EDA software will finally synthesize. Maybe lighting a light and running a horse is fine. This is why many rookies are still a rookie after learning for a long time. So why is FPGA "programmable"? First, let's understand what "cheng" is. The revelation "Cheng" is nothing but a bunch of 01 codes with a certain meaning.
Programming is actually writing these 01 codes. It's just that we now have a lot of development tool calculations or other operations. Therefore, the software is one by one. Usually, these 01 codes are not written directly, but are written in the form of high-level languages, and finally converted into this 01 code by the development tool. For software programming, the processor will have a special decoding circuit to translate these 01 codes into various control signals one by one, and then control its internal circuit to complete the reading one by one, because the operation of the software is completed step by step. The programmable nature of FPGA also relies on these 01 codes to realize the change of its functions, but the difference is that the reason why FPGA can complete different functions is not to translate the 01 codes like software to control an arithmetic circuit. None of these things.
There are three main parts in FPGA: programmable logic unit, programmable wiring and programmable IO module. What is a programmable logic unit? Its basic structure consists of a 4-input or 6-input 1-output "truth table" made of a certain memory (SRAM, FLASH, etc.) plus a D flip-flop. Any 4-input 1-output combinational logic circuit has a corresponding "truth table". Similarly, if a 4-input 1-output "truth table" is made of such a memory, it is only necessary to modify its "truth table". "The internal value can be equivalent to any combinational logic with 4 inputs and 1 output. What are these "truth table" internal values? It's just those 01 codes. What if you want to implement sequential logic circuits? This is not a D flip-flop, any sequential logic can be converted into a combinational logic + D flip-flop to complete. But after all, it only implements a logic circuit with 4 inputs and 1 output. Usually, the scale of the logic circuit is quite large.
then what should we do? At this time, you need to use the programmable connection. There are many memory-controlled link points on these lines, and by overwriting the corresponding memory values, it is possible to determine which lines are connected and which are disconnected. This can combine many programmable logic cells to form large logic circuits. The last is programmable IO, which is actually something that must be paid attention to when FPGA is used as a chip level.
Any chip must have input pins and output pins. There are programmable IOs that can arbitrarily define a non-dedicated pin (there are special non-user-available pins for testing and downloading in the FPGA) as input or output, and can also set the IO level standard. In a word, the reason why FPGA is programmable is that it can be made into "truth tables" through special 01 codes, and these "truth tables" can be combined to realize large-scale logic functions.
Without understanding the internal structure of the FPGA, you cannot understand how the final code changes into the FPGA. There is no in-depth understanding of how to make full use of FPGAs. Today's FPGA not only has the three blocks mentioned above, but also has many dedicated hardware functional units. How to make good use of these units to realize complex logic circuit design is an obstacle that must be overcome on the way from a rookie to a master. And all of this, or must start from understanding the internal logic of FPGA and its working principle.
2. Wrong understanding of HDL language, no matter how you look at it, you can't see the hardware structure
The full English name of HDL language is: Hardware Deion Language, pay attention to the word Deion, not Design. Why do foreigners use the word Deion instead of Design? Because HDL is really not used to design hardware, but only to describe hardware. The word description accurately reflects the essence of the HDL language. The HDL language is nothing but a textual representation of a known hardware circuit, and it just describes the future circuit in a textual form. Before writing the language, the hardware circuit should have been designed. Language simply translates this design into a literal form of expression. But many people don't understand it. Since the hardware has been designed, it's done directly to the production department. Why convert it into a textual expression and then go through the troublesome process of EDA tools? In fact, this is the problem that many rookies do not understand the abstraction level of design. Any design includes clothing, machinery, and advertising design. There is a problem of abstraction level. Take advertising design as an example, the initial design may be just a concept, and designing this concept is just an idea, and it is far from the final advertisement.
Hardware design also has different levels of abstraction, each of which requires design. The highest level of abstraction is the algorithm level, followed by the architecture level, register transfer level, gate level, and physical layout level. The advantage of using HDL is that we have already designed a circuit at the register transfer level, then the HDL description will be converted into text form, and the rest of the conversion to a lower level can be done by the EDA tool, which is a great deal. Reduced workload. This is the synthesizable concept, that is to say, the description of the hardware unit at this abstraction level can be understood by the EDA tool and transformed into the underlying gate-level circuit or circuits of other structures.
In FPGA design, this is described in HDL language in terms of abstraction level, which can be transformed into the realization form of FPGA internal logic function described in Question 1 through FPGA development software. HDL can also describe a higher level of abstraction such as algorithm level or architecture level, but currently limited by the development of EDA software, EDA software cannot understand such a high level of abstraction, so the abstraction level described by HDL cannot be transformed into At a lower level of abstraction, this is also called non-synthesizable. Therefore, when reading or writing HDL language, especially synthesizable HDL, you should not see the language itself, but the corresponding hardware circuit structure behind the language. If the HDL you see is always a piece of code, then such a person will never get rid of the fate of a rookie. If the code you see is no longer a line of code but a piece of hardware modules, then congratulations on leaving the rookie level and entering the less rookie level.
3. The FPGA itself is nothing, everything is outside the FPGA, which is probably the most difficult place for many rookies to learn FPGA
Who are FPGAs for? Many schools explain that it is for students majoring in microelectronics or integrated circuit design. In fact, this is just because many schools are limited by funds and cannot afford professional integrated circuit design tools and use FPGA tools instead. In fact, FPGAs are used by engineers who design electronic systems. These engineers usually use existing chips to complete an electronic device, such as base stations, set-top boxes, video surveillance equipment, etc. When the existing chip cannot meet the needs of the system, it is necessary to use FPGA to quickly define a usable chip.
As mentioned earlier, the FPGA cannot contain some "truth tables", triggers, various connections and some hardware resources. When an electronic system engineer uses an FPGA to design, it is nothing more than considering how to combine these future resources to achieve certain logic functions. It's just that, instead of having to worry about whether the final chip can be manufactured like IC design engineers do. In essence, it is no different from combining existing chips into different electronic systems, but it only needs to pay attention to lower-level resources. It is easy to use FPGA, because it is nothing more than those resources. After understanding the first two points, it is possible to create an experiment board, run experiments, and do something simple. To really make good use of FPGA, it is far from enough to know some FPGA knowledge. Because in the end, how to combine the resources in the FPGA and what kind of functions can be realized to meet the needs of the system, it is necessary to know more and more extensive knowledge.
At present, the application of FPGA is mainly in three directions:
The first direction: the traditional direction is mainly used for high-speed interface circuit design of communication equipment. This direction mainly uses FPGA to process high-speed interface protocols and complete high-speed data transceiver and exchange. Such applications usually require the use of FPGAs with high-speed transceiver interfaces. At the same time, designers are required to understand high-speed interface circuit design and high-speed digital circuit board-level design, have EMC/EMI design knowledge, and have a good analog circuit foundation. signal integrity issues that arise during the process. The first and most widely used application of FPGA is in the field of communication. On the one hand, the field of communication requires a high-speed communication protocol processing method. On the other hand, the communication protocol is modified at any time. Therefore, FPGAs that can flexibly change functions have become the first choice. More than half of FPGA applications so far are also in the communications industry.
The second direction: It can be called the direction of digital signal processing or the direction of mathematical calculation, because to a large extent this direction has gone far beyond the scope of signal processing. For example, as early as 2006, I heard that Laomei used FPGA for financial data analysis, and later saw a case of using FPGA for medical data analysis. In this direction, FPGA designers are required to have a certain mathematical foundation, be able to understand and improve more complex mathematical algorithms, and make use of various resources within the FPGA to turn them into actual operational circuits. At present, the fields of wireless signal processing, channel coding and decoding, and image signal processing in the field of communication are really put into practice. Research in other fields is being carried out. Learn about this stuff. However, recently, it has been found that many PhDs in electrical engineering and computer science in Europe and the United States have transferred to the financial industry to carry out financial signal processing. I believe that with the increase in the number of transferees, the mathematical computing functions of FPGA in other fields will be better displayed. Also intend to do some research in these areas. However, those who study finance and medicine in China rarely use mathematics, let alone using FPGA to help them complete mathematical operations. This issue can only be discussed again.
The third direction: the so-called SOPC direction, in fact, strictly speaking, this is already within the scope of FPGA design, but it is just the underlying hardware environment of an embedded system built on the FPGA platform, and then the designer is mainly on it. For embedded software development only. The design is fairly minimal when it comes to the design of the FPGA itself. But if it involves the need to do special algorithm acceleration in FPGA, the knowledge of the second direction is actually needed, and if you need to design a dedicated interface circuit, you need to use the knowledge of the first direction. As far as the current SOPC direction is far from the first and second directions, the main reason is that SOPC is mainly based on FPGA, or a "soft" processor is implemented in the resources inside the FPGA, or a "soft" processor is embedded in the FPGA. processor core. However, most embedded designs are based on software. Based on the existing hardware development, the interfaces in most cases have been standardized, and it does not require such large FPGA logic resources to design complex interfaces.
Moreover, it seems that the development tools related to SOPC are still very imperfect, and various embedded processor development tools represented by ARM have already been deeply rooted in the hearts of the people. Most SOC chips with ARM as the core provide most of the standard interfaces , A large number of series of single-chip microcomputer/embedded processors provide hardware acceleration circuits required by related industries, and there are indeed very few occasions that require special customized hardware.
It is usually in some special industries that there is a very urgent need in this regard. Even if Xilinx currently adds ARM's hard core to the FPGA, I believe that the current situation will not change much. Don't forget that many old-fashioned 8-bit microcontrollers are still mixed in the embedded field. Embedded is not mainly based on hardware differences. More depends on the difference of software to reflect the value.
Once optimistic about the idea of ​​cypress's Psoc. Different from the SOPC series, Psoc's ideological history records that a small piece of FPGA is embedded in the SOC chip, so it can actually meet the small hardware interface differences of the embedded, such as a certain application requires 4 USBs, and the usual processor It will not provide so many, so you can use such a FPGA to provide more USB interfaces. The other application, which requires 6 UARTs, can also be done in the same way.
For embedded design companies, they only need to stock one kind of chip, which can meet various small differences in these designs. Its main differentiation is still done through software. But at present cypress is too closed, if it uses ARM as the processor core, with its complete tool chain. At the same time, it is very promising to open IP cooperation and let a large number of third parties provide IP design for it. But the current cypress life is not easy, and Psoc's ideas don't know when it will shine.
The fourth direction: knowledge of digital logic is fundamental. No matter which direction FPGA is in, it is inseparable from the support of digital logic knowledge. FPGAs are simply a way of implementing digital logic. If there is a problem with even the most basic knowledge of digital logic, the desire to learn FPGA is just a castle in the air. And this is precisely the problem that many rookies are most reluctant to face. Digital logic is the professional basic knowledge of any electrical and electronic major, and it is also a course that must be learned well. Many people are nothing more than studying, taking a test, and finishing.
If you can't master the knowledge of digital logic and develop good design habits, learning FPGA is still in the fog and looking at the moon in the end, and it will always be empty. The above four points are just my conclusion that the rookies are most likely to go astray when learning FPGA. The learning of FPGA is actually like learning Go. It is easy to learn how to move on the chessboard, but it is even more difficult to become a master. In order to become a godlike player like Lee Chang-ho, in addition to hard research, I am afraid that he really needs a little talent.
Highlights:
1. To get started, you must first master HDL (HDL=verilog+VHDL)
The first sentence is: If you haven't learned mathematics and electricity, learn mathematics and electricity first. Then you can choose verilog or VHDL. If you have the basis of C language, it is recommended to choose VHDL. Because verilog is so much like C, it's easy to get confused, and you end up spending a lot of time trying to differentiate the two languages ​​rather than learning how to use it. Of course, if you can turn your thinking around, you can also choose verilog. After all, verilog is used more in China.
Next, first find this example to copy the code. The meaning of copying code is to be familiar with syntax rules and compilers (the compilers here are silicon compilers, also called synthesizers, commonly used compilers are: Quartus, ISE, Vivado, Design Compiler, Synopsys' VCS, iverilog, Lattice's Diamond, Microsemi/Actel's Libero, Synplify pro), then imitate and write, and finally write without reading a book. After compiling the code, open the RTL diagram to see what kind of circuit is synthesized.
HDL is a hardware description language, which highlights the characteristics of hardware, so we should think about HDL with digital thinking instead of using C language or other high-level languages. If you can't understand this sentence, you can read "What is hardware and what is software". At this stage, the recommended textbooks are "Verilog Legends", "Verilog HDL Advanced Digital Design" or "VHDL for Logic Synthesis". If you can write a three-stage state machine without reading a book, you can enter the next stage.
In addition, you must prepare Verilog or VHDL official documents, "verilog_IEEE Official Standard Manual-2005_IEEE_P1364", "IEEE Standard VHDL Language_2008", so that you can check it when you encounter some grammar problems.
2. Independently complete small and medium-scale digital circuit design
Now, you can design some digital circuits, such as traffic lights, electronic organs, DDS, etc. The recommended textbook is Xia Lao's "Verilog Digital System Design Tutorial" (third edition). At this stage, what you have to do is: give you a specification requirement or timing diagram, and you can design a circuit in HDL to implement it. Here you need a development board, you can choose Altera's cyclone IV series, or Xilinx's Spantan 6. Don't buy a development board before you have mastered HDL, because it's useless if you buy it. Here you don't need to download the code every time you compile and pass, we use modelsim to simulate (in addition to QuestaSim, NC verilog, Diamond's Active-HDL, VCS, Debussy/Verdi and other simulation tools), if the simulation fails, then you don't need to download Yes, definitely not. Here you can master a simple testbench first. The recommended textbook is "WRITING TESTBENCHES Functional Verification of HDL Models".
3. Master design methods and design principles
You may find that your synthesized circuit, while correct, has many caveats. At this time, you have to learn to synchronize design principles, optimize circuits, whether to give priority to speed or area, how to design a clock tree, how to synchronize two clocks with different frequencies, and so on. The recommended textbooks are "FPGA Authoritative Guide", "IP Core - Digital Logic Design Ideas", and "Altera FPGA/CPLD Design" Second Edition Basic and Advanced. Learn to speed up compilation (incremental compilation, LogicLock), static timing analysis (timequest), and embedded logic analyzer (signaltap), even if it is cleared. If there is something you don't understand, you can skip it temporarily, because this part requires a lot of practice to have a deeper understanding.
4. Learn to improve development efficiency
Because the editor functions of Quartus and ISE are too weak, the development efficiency is affected. Therefore, it is recommended to use the function of code snippets in the Sublime text editor to reduce repetitive labor. Modelsim is also a commonly used simulation tool. Learn TCL/TK to write your own DO file, which makes the simulation automated. The recommended textbook is "TCL/TK Introductory Classic". You might back up your code manually, but the pros use version controllers, so in order to be productive, mastering GIT is a must. The file comparer Beyond Compare is also a more commonly used tool. In addition, you can also use System Verilog instead of testbench, which will be more efficient. If you are doing IC verification, you must master System Verilog and Verification Methodology (UVM). The recommended textbooks are "Writing Testbenches using SystemVerilog", "The UVM Primer", "System Verilog1800-2012 Grammar Manual".
After mastering TCL/TK, you can learn virtual Jtag (ISE also has similar tools) to make your own debugging tools. In addition, if you have time, it is best to learn python. Script, meant once and for all.
5. Strengthen the theoretical foundation
At this time, you can already use FPGA, but there are still many things you can't do (for example, FIR filter, PID algorithm, OFDM, etc.), because the theory is not well learned. I roughly divide it into several directions for your reference, followed by the theoretical lessons to be mastered.
Signal Processing - Signals and Systems, Digital Signal Processing, Digital Image Processing, Modern Digital Signal Processing, Blind Signal Processing, Principles of Adaptive Filters, Radar Signal Processing
Interface applications - such as: UART, SPI, IIC, USB, CAN, PCIE, Rapid IO, DDR, TCP/IP, SPI4.2 (10G Ethernet interface), SATA, optical fiber, DisplayPort
Wireless Communication - Signals and Systems, Digital Signal Processing, Communication Principles, Fundamentals of Mobile Communication, Stochastic Processes, Information Theory and Coding
CPU Design - Principles of Computer Composition, SCM, Computer Architecture, Compilation Principles
Instrumentation - analog electronic technology, high frequency electronic circuit, electronic measurement technology, principle and application of intelligent instrument
Control System - Automatic Control Principle, Modern Control Theory, Process Control Engineering, Fuzzy Controller Theory and Application
Compression, Coding, Encryption - Number Theory, Abstract Algebra, Modern Coding Technology, Information Theory and Coding, Introduction to Data Compression, Applied Cryptography, Audio Information Processing Technology, Principles of Digital Video Coding Technology
Now you find that the original FPGA will involve so much knowledge, you can choose a direction of interest, but the knowledge of several of them is likely to be used in the work, so the more theory you learn, the better. Maths and English are inevitable if you're going to the next level.
6. Learn to use MATLAB simulation
When designing FPGA algorithms, MATLAB is used more or less, such as CRC coefficient matrix, digital filter coefficients, various tables and text processing. In addition, MATLAB can also be used to debug HDL (compare the calculation results of MATLAB with the step-by-step calculations calculated with HDL, you can know where the problem is). The recommended textbooks are "MATLAB Collection" and Du Yong's "MATLAB and FPGA Implementation of Digital Filters".
7. Adequate practice
At this time, you have read the chip manual at least several times (available on the official website), and then you can do a certain amount of practice according to your own direction (during this period, you should maintain a good code style, increase the readability of component instantiation statements, and draw flowcharts /sequence diagrams, the habit of writing documentation). For example, the communication type can be used as a modulation and demodulation algorithm, and the instrument type can be used as a bus analyzer, etc. However, these algorithms are only given a formula and a block diagram in the book, which is very far from the actual, and you may even feel that the things in the book are superficial. Then, you can find some relevant information on CNKI, Baidu Wenku, EETOP forum, opencores, ChinaAET, Q group sharing, and blog (friends outside the school can buy a CNKI account on Taobao). In fact, when you reach this stage, you have reached the professional level, and you can learn more about some cutting-edge technologies when you have time, which will help your career planning.
At work, you may need to pay attention to many protocols and industry standards. Protocols can be found on EETOP, and standards (such as national standards GB and GB/T, international standards ISO) recommend "Standard Network" and "Standard Sharing Network" .
8. Image processing (this part is only written for friends who want to learn image processing, and it is also a route from shallow to deep)
Photoshop. Spend one or two weeks learning PS, have a general understanding of image processing, know basic concepts such as various image formats, histograms, hues, channels, filters, stitching, etc., and be able to use it. This part is the 0 basis, the purpose is to let everyone have a perceptual understanding of image processing, rather than derivation of various formulas at the beginning. Recommend "Photoshop CS6 complete self-study tutorial".
Image processing based on MATLAB or OpenC++V. Those with C/C++ foundation can learn OpenCV, otherwise, it is recommended to learn MATLAB. At this stage, as long as you learn to simply call functions, you don't need to delve into the details of the implementation for the time being. Recommended "Digital Image Processing Matlab Edition", "Learning OpenCV".
The basic theory of image processing. The theory of this part requires the basics of advanced numbers, complex variables, linear algebra, signals and systems, digital signal processing, etc. If the basics are not good, it is recommended to supplement the basics first. If you don’t understand the theory, you can put it aside for a while, and maybe you will naturally get enlightened after you learn it. "Digital Image Processing" is recommended.
FPGA-based image processing. Apply the theory learned earlier to FPGA. If you have the level of the previous seventh stage, you will easily complete the image algorithm design independently (image processing is inseparable from the interface, as mentioned in the fifth stage above ). Recommended "FPGA-based Embedded Image Processing System Design", "FPGA-based Digital Image Processing Principles and Applications".
Delve further into mathematics. To go to a higher level in the algorithm, more mathematics is necessary, so it is recommended to learn real analysis, general analysis, wavelet analysis, etc.
(The following two stages are introduced to interested friends.)
9. The end of digital electricity is analog electricity
Now things inside the FPGA are not difficult for you, but when the signal goes out of the FPGA, you can't control it. At this time, you must learn to model electricity. For example: circuit analysis, analog electronic technology, high-frequency electronic circuits, PCB design, EMC, SI, PI, etc., if you can design an FPGA development board with two DDR3 pieces, even if you pass the customs.
10. There is no end to learning
If you can reach this level, you are already very good, but there is still a lot to learn, because FPGA often interacts with CPU, which means that you have to communicate with software engineers frequently, so you also need to know some software knowledge. For example, ARM (Xilinx's ZYNQ and Altera's SOC will use ARM's hard core), DSP, Linux, Android, and host computers (QT, C#, JAVA) can all learn, anyway, there is no end to learning.
11. Other issues
a. Why is it not recommended to learn soft cores such as NIOS II and MicroBlaze?
The price/performance ratio is not high, and the general soft core performance is about the same as Cortex M3 or M4. It is very uneconomical to use something as expensive as an FPGA to make a CPU with average performance. Might as well add another M3.
Adding soft cores may affect other logic functions. This is in the case of insufficient resources, coupled with the soft core, which makes the layout and routing very difficult.
The soft core is not open source, and when there is a bug, it is not easy to debug.
Rarely used in engineering, most likely will not come in handy.
b. Why is ZYNQ or SOC not recommended for 0 basic learning?
It is easy for people to have a sympathy. Tongtong psychology means that a person can cover up and make up for his own shortcomings in this area by exaggerating the excellence of people who are close to him, so as to obtain a psychological balance. I'm learning something great, and then I feel like I'm great, but it's just an illusion.
The entry should learn as simple as possible, either concentrate on learning ARM, or concentrate on learning FPGA. This makes it easier to have a sense of accomplishment and boost confidence.
The application fields of ZYNQ and SOC are not wide, and many people have not heard of this kind of thing, which leads to the disadvantage of job hunting.
Development tools take a long time to compile and waste more time.
Most of the work is only responsible for one aspect, which means that the other aspect is likely to be useless.
c. Why do so many IP cores still need to write HDL?
Students who ask this kind of question are generally students who have never made a product or encountered an engineering problem.
IP cores are not a panacea and cannot meet all needs.
Use closed-source IP cores as little as possible. Once there is a problem, this kind of black box is likely to make the product difficult to produce.
A deeper understanding of the bottom level allows better use of the higher level. This rule can be applied to all programming languages.
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