ADI Quad High Performance Low Noise Buck Regulator - Detailed Description of ADP5014

ADI's ADP5014 integrates four high-performance, low-noise buck regulators in a 6 mm & TImes; 6 mm 40-lead LFCSP package with high-side and low-side power metal-oxide-semiconductor field-effect transistors (MOSFETs) integrated in all channels Channel 1 and Channel 2 provide both 2 A or 4 A of programmable output current, and Channel 3 and Channel 4 provide both 1 A and 2 A of programmable output current. Other features include optional forced pulse width modulation (FPWM) / Power-saving mode (PSM), undervoltage output (UVO), active output discharge, and power good indication. Safety features include input undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), and thermal shutdown TSD (TSD). Input voltage 2.75V-6.0V, programmable output voltage 0.5V-0.9xVINx. Mainly used in RF transceiver, high speed analog-to-digital converter (ADC) / digital-to-analog converter (DAC), mixed signal ASIC , Field Programmable Gate Array (FPGA) and Processor Applications, Security and Monitoring, and Medical Applications. This article describes the main features of the ADP5014, functional block diagrams, typical application circuits, and the main features of the evaluation board ADP5014-EVALZ, circuit diagrams, bill of materials, and PCB. design diagram.

The ADP5014 combines four high performance, low noise buckregulators in a 40-lead LFCSP package. Relying on its lowoutput noise (~25 μVrms when VOUT ≤ VREF), the low noisebuck regulator enables the powering up of the noise sensiTIvesignal chain products.

All channels in the ADP5014 integrate high-side and low-side power metal-oxide semiconductor field effect transistors (MOSFET). Channel 1 and Channel 2 deliver a programmable output current of 2 A or 4 A. Combining Channel 1 and Channel 2 in a parallel configuraTIon provides a single outputwith up to 8 A of current.

Channel 3 and Channel 4 deliver a programmable output currentof 1 A or 2 A. Combining Channel 3 and Channel 4 in a parallelconfiguraTIon can provide a single output with up to 4 A of current.

Alternatively, the sequence mode has one grouped precision enable signal with programmable power-upand power-down delay timers on each rail for specific railsequence requirements.

The switching frequency of the ADP5014 can be programmedor synchronized to an external clock from 500 kHz to 2.5 MHz. The ADP5014 offers other key features like selective forcedpulse width modulation (FPWM)/power saving mode (PSM), an undervoltage output (UVO), Active output discharge, and apower-good flag. Other safety features include input undervoltagelockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP) and thermal shutdown (TSD).

Main features of ADP5014:

Input voltage range: 2.75 V to 6.0 V
Programmable output voltage range: 0.5 V to 0.9 × PVINx
Low output noise: ~25 μVrms when VOUT ≤ VREF±1.0% output accuracy over full temperature range500 kHz to 2.5 MHz adjustable switching frequency
Power regulation
Channel 1 and Channel 2: programmable 2 A/4 A syncbuck regulators, or single 8 A output in parallel
Channel 3 and Channel 4: programmable 1 A/2 A syncbuck regulators, or single 4 A output in parallel
Flexible parallel operation
Precision enable with 0.6 V threshold
Manual or sequence mode for power-up and power-downsequence
Selective FPWM or PSM operation mode
Precision undervoltage comparator
Frequency synchronization input or output
Active output discharge switch
Power-good flag on selective channels via factory fuse
UVLO, OVP, OCP, and TSD protection
40-lead, 6 mm × 6 mm LFCSP package
−40 °C to +125 °C junction temperature

ADP5014 application:

RF transceiver, high speed analog-to-digital converter
(ADC)/digital-to-analog converter (DAC), mixed signal ASIC
FPGA and processor applications
Security and surveillance
Medical applications

Figure 1. Functional block diagram of the ADP5014

Figure 2. ADP5014 Typical Application Circuit Diagram (1)

Figure 3. Typical application circuit diagram for ADP5014 (2): FPGA application, 1.2MHz switching frequency, sequential enable mode

Figure 4. Typical application circuit diagram for ADP5014 (2): RF transceiver application, 1.2MHz switching frequency, sequential enable mode

Evaluation Board ADP5014-EVALZ

This user guide describes the evaluation of the ADP5014 and includes detailed schematics and printed circuit board (PCB) layouts.

The ADP5014-EVALZ evaluation board combines four high performance buck regulators in a 40-lead LFCSP package to meet the demanding performance and board space requirements.

Full details on the ADP5014 regulator are provided in the ADP5014 data sheet, available from Analog Devices, Inc. Consult the data sheet in conjunction with this user guide when working with this evaluation board.

Main features of the evaluation board ADP5014-EVALZ:

Full featured evaluation board for the ADP5014
Compact solution size
4-layer high glass transition temperature (TG) PCB for superior thermal performance
Convenient connections through vertical printed circuit tail pin headers
Supply voltage
2.75 V to 6.0 V for PVINx
Mode option to select manual or sequence enable
Mode option to select PSM or FPWM operation
Programmable switching frequency from 500 kHz to 2.5 MHz
Frequency synchronization input or output

Figure 5. Outline of the evaluation board ADP5014-EVALZ

Figure 6. Evaluation Board ADP5014-EVALZ Circuit Diagram Evaluation Board ADP5014-EVALZ Bill of Materials (BOM):

Figure 7. Evaluation Board ADP5014-EVALZ PCB Design (1)

Figure 8. Evaluation Board ADP5014-EVALZ PCB Design (2)

Figure 9. Evaluation Board ADP5014-EVALZ PCB Design (3)

Figure 10. Evaluation Board ADP5014-EVALZ PCB Design (4)
For details, please see:

with
ADP5014-EVALZ-UG-1137.pdf

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